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High Speed CMOS Optocouplers Technical Data
HCPL-7100 HCPL-7101
Features
* 1 m CMOS IC Technology * Compatibility with All +5 V CMOS and TTL Logic Families * No External Components Required for Logic Interface * High Speed: 15 MBd (HCPL-7100) and 50 MBd (HCPL-7101) Guaranteed * Low Power Consumption * Safety Approvals UL 1577 (3750 Vac/1 Min) VDE 0884 (VIORM = 848 V peak) CSA * 3-State Output * 3750 Vac/1 Minute Dielectric Withstand * High Common Mode Transient Immunity
Description
The HCPL-7100/7101 optocoupler combines the latest CMOS IC technology, a new high-speed high-efficiency AlGaAs LED, and an optimized light coupling system to achieve outstanding performance with very low power consumption. It requires only two bypass capacitors for complete CMOS/TTL compatibility. Basic building blocks of the HCPL-7100/7101 are a CMOS LED driver IC, an AlGaAs LED, and a CMOS detector IC. A CMOS or TTL logic input signal controls the LED driver IC which supplies current to the LED. The detector IC incorporates an integrated photodiode, a high-speed transimpedance amplifier and a voltage comparator with hysteresis. The 3-state output is CMOS and TTL
compatible and is controlled by the output enable pin, VOE. The HCPL-7100/7101 consumes very little power, due to the CMOS IC technology and the light coupling system. The entire optocoupler typically uses only 10 mA of supply current, including the LED current. World-wide safety approval and 3750 Vac/1 minute dielectric withstand is achieved with our patented "light-pipe" optocoupler packaging technology. The HCPL-7100/7101 provides he user with an easy-to-use CMOS or TTL compatible optocoupler ideally suited for a variety of applications where high speed and low power consumption are desired.
Applications
* Multiplexed Data Transmission * Computer-Peripheral Interface * Microprocessor System Interface * Digital Isolation for A/D, D/A Conversion * Instrument Input/Output Isolation * Motor Control * Power Inverter
Schematic
TRUTH TABLE (POSITIVE LOGIC) INPUT H L H L ENABLE H H L L OUTPUT Z Z H L
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.
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5965-3578E
Ordering Information
HCPL-710x 0 = 15 MBd Minimum Data Rate 1 = 50 MBd Minimum Data Rate Option yyy 300 = Gull Wing Surface Mount Lead Option 500 = Tape/Reel Package Option (1 k min.) Option data sheets available. Contact your Hewlett-Packard sales representative or authorized distributor for information.
Package Outline Drawings
Standard DIP Package
9.40 (0.370) 9.90 (0.390) 8 7 6 5 TYPE NUMBER HP XXXX YYWW RU PIN ONE 1.19 (0.047) MAX. 1 2 3 4 UL RECOGNITION DATE CODE 6.10 (0.240) 6.60 (0.260) 7.36 (0.290) 7.88 (0.310) 0.20 (0.008) 0.33 (0.013)
5 TYP.
1.78 (0.070) MAX.
4.70 (0.185) MAX.
1 2
VDD1 VI * GND1
VDD2 8 VOE 7 VO 6 GND2 5
0.51 (0.020) MIN. 2.92 (0.115) MIN.
3 4
0.76 (0.030) 1.40 (0.055)
0.65 (0.025) MAX. 2.28 (0.090) 2.80 (0.110) * PIN 3 THE ANODE OF THE INTERNAL LED AND * PIN 3 IS IS THE ANODE OF THE INTERNAL LED AND MUST BE LEFT UNCONNECTED FOR GUARANTEED MUST BE LEFT UNCONNECTED FOR GUARANTEED DATA SHEET PERFORMANCE. DATA SHEET PERFORMANCE. DIMENSIONS IN MILLIMETERS AND (INCHES). DIMENSIONS IN MILLIMETERS AND (INCHES).
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OPTOCOUPLERS
Gull Wing Surface Mount Option 300*
PIN LOCATION (FOR REFERENCE ONLY) 9.65 0.25 (0.380 0.010)
8 7 6 5
1.02 (0.040) 1.19 (0.047)
TYPE NUMBER DATE CODE
4.83 TYP. (0.190) HP XXXX YYWW RU 6.350 0.25 (0.250 0.010) 9.65 0.25 (0.380 0.010)
MOLDED
1
2
3
4
UL RECOGNITION
1.19 (0.047) 1.78 (0.070) 9.65 0.25 (0.380 0.010) 7.62 0.25 (0.300 0.010)
0.380 (0.015) 0.635 (0.025)
1.19 (0.047) MAX.
1.780 (0.070) MAX.
4.19 MAX. (0.165)
0.20 (0.008) 0.33 (0.013)
1.080 0.320 (0.043 0.013) 2.540 (0.100) BSC
0.51 0.130 (0.020 0.005)
0.635 0.25 (0.025 0.010) 12 NOM.
DIMENSIONS IN MILLIMETERS (INCHES). TOLERANCES (UNLESS OTHERWISE SPECIFIED): xx.xx = 0.01 xx.xxx = 0.005
LEAD COPLANARITY MAXIMUM: 0.102 (0.004)
*Refer to Option 300 data sheet for more information.
Maximum Solder Reflow Thermal Profile
260 240 220 200 180 160 140 120 100 80 60 40 20 0 0 1 T = 145C, 1C/SEC T = 115C, 0.3C/SEC
TEMPERATURE - C
T = 100C, 1.5C/SEC
2
3
4
5
6
7
8
9
10
11
12
TIME - MINUTES (NOTE: USE OF NON-CHLORINE ACTIVATED FLUXES IS RECOMMENDED.)
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The HCPL-7100/1 has been approved by the following organizations: UL Recognized under UL 1577, Component Recognition Program, File E55361.
Insulation and Safety Related Specifications
Parameter Symbol Value Units Min. External Air Gap L(IO1) 7.4 mm (External Clearance) Min. External Tracking L(IO2) 8.0 mm Path (External Creepage) Min. Internal Plastic 0.5 mm Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group CTI 175 V Conditions Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Through insulation distance, conductor to conductor, usually the direct distance between the photoemitter and photodetector inside the optocoupler cavity DIN IEC 112/VDE 0303 PART 1
IIIa
Material Group (DIN VDE 0110, 1/89, Table 1)
Option 300 - surface mount classification is Class A in accordance with CECC 00802.
VDE 0884 (06.92) Insulation Characteristics
Description Installation classification per DIN VDE 0110, Table 1 for rated mains voltage 300 V rms for rated mains voltage 600 V rms Climatic Classification Pollution Degree (DIN VDE 0110, Table 1)* Maximum Working Insulation Voltage Input to Output Test Voltage, Method b** VPR = 1.875 x VIORM, Production test with tp = 1 sec, Partial discharge < 5 pC Input to Output Test Voltage, Method a** VPR = 1.5 x VIORM, Type and sample test, tp = 60 sec, Partial discharge < 5 pC Highest Allowable Overvoltage** (Transient Overvoltage, tTR = 10 sec) Safety-limiting values (Maximum values allowed in the event of a failure, also see Figure 15) Case Temperature Input Power Output Power Insulation Resistance at TS, VIO = 500 V Symbol Characteristic I-IV I-III 40/85/21 2 848 1591 Unit
VIORM VPR
V peak V peak
VPR VTR
1273 6000
V peak V peak
TS PS,INPUT PS,OUTPUT RS
175 80 250 1 x 1012
C mW mW
*This part may also be used in Pollution Degree 3 environments where the rated mains voltage is 300 V rms (per DIN VDE 0110). **Refer to the front of the optocoupler section in the current catalog for a more detailed description of VDE 0884 and other product safety requirements. Note: Optocouplers providing safe electrical separation per VDE 0884 do so only within the safety-limiting values to which they are qualified. Protective cut-out switches must be used to ensure that the safety limits are not exceeded.
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OPTOCOUPLERS
Regulatory Information
CSA Approved under CSA Component Acceptance Notice #5, File CA 88324.
VDE Approved according to VDE 0884/06.92
Absolute Maximum Ratings
Parameter Storage Temperature Ambient Operating Temperature Supply Voltages Input Voltage Output Voltage Output Enable Voltage Average Output Current Package Power Dissipation Lead Solder Temperature (1.6 mm Below Seating Plane, 10 sec.) Reflow Temperature Profile Symbol TS TA VDD1,2 VI VO VOE IO PPD TLS Min. -55 -40 0.0 -0.5 -0.5 -0.5 Max. 125 85 5.5 VDD1 + 0.5 VDD2 + 0.5 VDD2 + 0.5 25 220 260 Unit C C V V V V mA mW C
See Package Outline Drawings Section
Recommended Operating Conditions
Parameter Operating Temperature Supply Voltages Logic High Input Voltage Logic Low Input Voltage Logic High Output Enable Voltage Logic Low Output Enable Voltage Input Signal Rise and Fall Times TTL Fanout Symbol TA VDD1,2 VIH VIL VOEH VOEL tr, tf N Min. -40 4.5 2.0 0.0 2.0 0.0 Max. 85 5.5 VDD1 0.8 VDD2 0.8 1 6 Unit C V V V V V ms Standard Loads Output in high impedance state Output enabled Test Conditions
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Electrical Specifications
Guaranteed across recommended operating conditions. Test conditions represent worst case values for the parameter under test. Test conditions that are not specified can be anywhere within their operating range. All typicals are at 25C and 5 V supplies unless otherwise noted.
Parameter Logic Low Input Supply Current Logic High Input Supply Current Logic Low Output Supply Current Logic High Output Supply Current Symbol IDD1L IDD1H IDD2L Min. Typ. 5.2 0.3 0.9 5.0 Max. 10.0 0.6 1.6 9.0 mA Unit mA mA Test Conditions VDD1 = 5.5 V VI = VIL VI = 4.5 V VI = 2.0 V VDD2 = 5.5 V VOE = VOEL VI = VIL VDD2 = 5.5 V VOE = VOEL IO = 0 mA VI = VIH VOE = 4.5 V VOE = 2.0 V A A VI = VDD1 or GND VDD1 = 5.5 V VOE = VDD2 or GND VDD2 = 5.5 V IO = -20 A V mA IO = -4.0 mA IO = -6.0 mA VDD2 = 4.5 V VO = 3.6 V VI = VIH VOE = VOEL IO = 20 A IO = 4.0 mA IO = 6.0 mA mA VDD2 = 4.5 V VO = 0.6 V VI = VIL VOE = VOEL VDD2 = 5.5 V VOE = VOEH VO = VDD2 or GND f = 1 MHz TA = 25C TA = 100C 0.7 pF f = 1 MHz 2 VI-O = 500 Vdc 4 2 VDD2 = 4.5 V VI = VIL VOE = VOEL VDD2 = 4.5 V VI = VIH VOE = VOEL 6 VDD2 = 5.5 V VDD1 = 5.5 V Fig. Note 1 1
IDD2H
5.2
9.0
mA
Tri-State Output Supply Current Input Current Output Enable Current Logic High Output Voltage
IDD2Z II IOE VOH -1 -1 4.4 4.0 3.7 IOH -7.5
5.1 5.6
9.0 10.0 1 1
mA
5.0 4.8 4.7 -25
Logic High Output Current
6
Logic Low Output Voltage
VOL
0.0 0.1 0.15
0.1 0.3 0.4
5
V
Logic Low Output Current
IOL
10.5
23
5
High Impedance State Output Current Input Capacitance Input-Output Input-Output Capacitance
IOZ
-5
5
A
CI RI-O CI-O 1012 1011
4.3 1013
pF
Resistance
*The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Characteristics Table (if applicable), your equipment level safety specification, or HP Application Note 1074, "Optocoupler Input-Output Endurance Voltage."
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OPTOCOUPLERS
Switching Specifications
Guaranteed across recommended operating conditions. Test conditions represent worst case values for the parameter under test. Test conditions that are not specified can be anywhere within their operating range. All typicals are at 25C and 5 V supplies unless otherwise noted.
Parameter Propagation Delay Time to Logic Low Output Symbol tPHL Device HCPL-7100 HCPL-7101 HCPL-7100 HCPL-7101 Propagation Delay Time to Logic High Output tPLH HCPL-7100 HCPL-7101 HCPL-7100 HCPL-7101 Pulse Width Distortion |tPHL- tPLH| PWD HCPL-7100 HCPL-7101 HCPL-7100 HCPL-7101 Data Rate HCPL-7100 HCPL-7101 Propagation Delay Skew Output Rise Time (10-90%) Output Fall Time (90-10%) Random Jitter tPSK tR HCPL-7101 HCPL-7100 HCPL-7101 tF HCPL-7100 HCPL-7101 RJ HCPL-7101 12 10 8 7 50 ps rms V1 = 0-5 V square wave, f = 25 MHz, input rise/ fall time = 5 ns. RL = 10 k, CL = 5 pF. TTL Threshold Levels. CL = 50 pF CMOS Signal Levels CL = 15 pF TTL Signal Levels CL = 50 pF CMOS Signal Levels CL = 15 pF TTL Signal Levels 12 6 12 6 ns CL = 50 pF CMOS Signal Levels 7 15 50 65 10 ns ns CL = 50 pF CMOS Signal Levels 10 7 9 2 27 28 Min. Typ. Max. 70 40 70 40 70 40 70 40 20 6 20 6 MBd % PWD < 30% 8 ns CL = 15 pF TTL Signal Levels ns CL = 50 pF CMOS Signal Levels 7, 9 6, 7 ns CL = 15 pF TTL Signal Levels ns CL = 50 pF CMOS Signal Levels 7, 8 5, 6 ns CL = 15 pF TTL Signal Levels Unit ns Test Conditions CL = 50 pF CMOS Signal Levels Fig. 7, 8 Note 5, 6
Propagation Delay Time From Output Enabled to Logic High Output Propagation Delay Time From Output Enabled to Logic Low Output
tPZH
13 12
ns ns ns ns
tPZL
11 10
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Switching Specifications (cont.)
Guaranteed across recommended operating conditions. Test conditions represent worst case values for the parameter under test. Test conditions that are not specified can be anywhere within their operating range. All typicals are at 25C and 5 V supplies unless otherwise noted.
Parameter Propagation Delay Time from Logic High to Output Disabled Symbol tPHZ Device Min. Typ. 12 12 Max. Unit ns ns Test Conditions CL = 50 pF CMOS Signal Levels CL = 15 pF TTL Signal Levels CL = 50 pF CMOS Signal Levels CL = 15 pF TTL Signal Levels VCM = 50 V VCM = 200 V VI = VIH VD > 3.2 V 13, 14 10 12 6 Fig. 12 Note 6
Propagation Delay Time from Logic Low to Output Disabled Common Mode Transient Immunity at Logic High Output Common Mode Transient Immunity at Logic Low Output Input Dynamic Power Dissipation Capacitance Output Dynamic Power Dissipation Capacitance
tPLZ
9 11
ns ns V/s
|CMH|
HCPL-7100 1000 HCPL-7101 2000
|CML|
HCPL-7100 1000 HCPL-7101 2000
V/s
VCM = 50 V VCM = 200 V
VI = VIL VD < 0.8 V
13, 14
10
CPD1
68
pF
11
CPD2
10
pF
11
Package Characteristics
Guaranteed across recommended operating conditions. Test conditions represent worst case value for the parameter under test. Test conditions that are not specified can be anywhere within their operating range. All typicals are at TA = 25C and 5 V supplies unless otherwise noted. Parameter Input-Output Momentary Withstand Voltage* Input-Output Resistance Input-Output Capacitance Sym. VISO Min. 3750 Typ. Max. Units V rms Test Conditions t = 1 min., RH < 50%, TA = 25C TA = 25C TA =100C f = 1 MHz VI-O = 500 Vdc Fig. Note 2, 3
RI-O CI-O
1012 1011
1013 0.7
pF
2 2
*The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Characteristics Table (if applicable), your equipment level safety specification or HP Application Note 1074 entitled "Optocoupler Input-Output Endurance Voltage."
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OPTOCOUPLERS
Notes: 1. The LED is OFF when the VI is high and ON when VI is low. 2. Device considered a two terminal device; pins 1-4 shorted together and pins 5-8 shorted together. 3. In accordance with UL 1577, for devices with minimum VISO specified at 3750 V rms, each optocoupler is proof-tested by applying an insulation test voltage greater than 4500 V rms for one second (leakage current detection limit II-O < 5 A). This test is performed before the method b, 100% production test for partial discharge shown in the VDE 0884 Insulation Characteristics Table. 4. CI is the capacitance measured at pin 2 (VI). 5. tPHL propagation delay is measured from the 50% level on the falling edge of the VI signal to the logic switching level of the VO signal. tPLH propagation delay is measured from the 50% level on the rising edge of the VI signal to the logic switching level of the VO signal. 6. The logic switching levels are 1.5 V for TTL signals (0-3 V) and 2.5 V for CMOS signals (0-5 V). 7. PWD is defined as |tPHL - tPLH|. %PWD (percent pulse width distortion) is equal to PWD in ns divided by symbol duration (bit length) in ns. 8. Minimum data rate is calculated as follows: %PWD/PWD where %PWD is typically chosen by the design engineer (30% is common). 9. tPSK is equal to the worst case difference in tPHL and/or tPLH that will be seen between units at the same temperature, supply voltage, and output load within the recommended operating condition range. 10. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VO > 3.2 V. CML is the maximum common mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common mode voltage slew rates apply to both rising and falling common mode voltage edges. 11. Unloaded dynamic power dissipation is calculated as follows: CPD * VDD2 * f + IDD * VDD where f is switching frequency in MHz.
Figure 1. Recommended Application Circuit.
Figure 2. Recommended Printed Circuit Board Layout.
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5.50 5.00 4.50 85 C 4.00 3.50
VO (V)
VDD1 = 5.0 V
-40 C 25 C
3.00 2.50 2.00 1.50 1.00 0.50 0 0 1.00 2.00 3.00 4.00 5.00 VI (V)
Figure 3. Typical Output Voltage vs. Input Voltage.
Figure 4. Typical Input Voltage Switching Threshold vs. Input Supply Voltage.
VDD2 = 5.0 V
VDD2 = 5.0 V
Figure 5. Typical Logic Low Output Voltage vs. Logic Low Output Current.
Figure 6. Typical Logic High Output Voltage vs. Logic High Output Current.
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OPTOCOUPLERS
Figure 7. Test Circuit for Propagation Delay, Rise Time and Fall Time.
VDD1 = 5.0 V VDD2 = 5.0 V
VDD1 = 5.0 V VDD2 = 5.0 V
Figure 8. HCPL-7101 Typical Propagation Delay vs. Temperature.
Figure 9. HCPL-7101 Typical Pulse Width Distortion vs. Temperature.
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Figure 10. Propagation Delay Skew Waveform.
Figure 11. Parallel Data Transmission Example.
Figure 12. Test Circuit for 3-State Output Enable and Disable Propagation Delays.
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OPTOCOUPLERS
VDD1 = 5.0 V VDD2 = 5.0 V TA = 25 C
Figure 14. Typical Common Mode Transient Immunity vs. Common Mode Transient Voltage.
OUTPUT, VO
VOL
Figure 13. Test Circuit for Common Mode Transient Immunity and Typical Waveforms.
400 OUTPUT POWER, PS INPUT POWER, PS
PS - POWER - mW
300
200
100
0
0
20 40 60 80 100 120 140 160 180 175 TA - TEMPERATURE - C
Figure 15. Dependence of Safety-Limiting Data on Ambient Temperature.
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HCPL-7100/7101 Application Information
The HCPL-7100/7101 is extremely easy to use. Because the optocoupler uses high-speed CMOS IC technology, the inputs and output are fully compatible with all +5 V TTL and CMOS logic. TTL or CMOS logic can be connected directly to the inputs and output; no external interface circuitry is required. As shown in Figure 1, the only external components required for proper operation are two ceramic bypass capacitors. Capacitor values should be between 0.01 F and 0.1 F. For each capacitor, the total lead length between both ends of the capacitor and the power-supply pins should not exceed 20 mm. Figure 2 illustrates the recommended printed circuit board layout for the HCPL-7100/7101.
value. PWD is defined as the difference between tPLH and tPHL and often determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of 20-30% of the minimum pulse width is tolerable; the exact figure depends on the particular application (RS232, RS422, T-1, etc.). Propagation delay skew, tPSK, is an important parameter to consider in parallel data applications where synchronization of signals on parallel data lines is a concern. If the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delays is large enough, it will determine the maximum rate at which parallel data can be sent through the optocouplers. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays, either tPLH or tPHL, for any given group of optocouplers which are operating under the same conditions (i.e., the same supply voltage, output load, and operating temperature). As illustrated in Figure 10, if the inputs of a group of optocouplers are switched either ON or OFF at the same time, tPSK is the difference between the shortest propagation delay, either tPLH or tPHL, and the longest propagation delay, either tPLH or tPHL.
As mentioned earlier, tPSK can determine the maximum parallel data transmission rate. Figure 11 is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through optocouplers. The figure shows data and clock signals at the inputs and outputs of the optocouplers. To obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast. Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. Figure 11 shows that there will be uncertainty in both the data and the clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice tPSK. A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. The HCPL-7101 optocoupler offers the advantages of guaranteed specifications for propagation delays, pulse-width distortion and propagation delay skew over the recommended temperature, and power supply ranges.
Propagation Delay, PulseWidth Distortion, and Propagation Delay Skew
Propagation delay is a figure of merit which describes how quickly a logic signal propagates through a system. The propagation delay from low to high (tPLH) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low (tPHL) is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low (see Figure 7). Pulse-width distortion (PWD) results when tPLH and tPHL differ in
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OPTOCOUPLERS

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